74LS04 — DATASHEET-ACCURATE INTERNAL SCHEMATIC (ONE OF SIX GATES) TI SN74LS04 · All resistor values nominal per SDLS029C datasheet · Schottky-clamped NPN transistors throughout VCC +5V GND A D_in GND clamp (neg. protection) R1 20kΩ VCC pullup B-C clamp Q1 multi-emitter emitter = input (TTL trick) R2 8kΩ B-C R3 1.5kΩ Q2 phase splitter R4 12kΩ Q3 bias R6 3kΩ R5 4kΩ Q4 base pulldown B-C clamp Q3 totem top R_out 120Ω D_out Schottky 120Ω+diode = LS output Y B-C clamp Q4 totem bottom ━━ dashed = Schottky B-C clamp diode Each NPN transistor has a Schottky diode across B-C, preventing saturation. This is the "LS" in 74LS — it's what makes switching fast without deep storage delay. TIMING: t_PLH = 9ns typ · t_PHL = 10ns typ · P_d = 2mW/gate A→HIGH: Q1 off → Q2 off → Q3 on, Q4 off → Y=HIGH (≥2.7V) | A→LOW: Q1 on → Q2 on → Q3 off, Q4 on → Y=LOW (≤0.5V) ① INPUT STAGE ② PHASE SPLITTER ③ TOTEM TOP ④ TOTEM BOTTOM V_OH ≥ 2.7V (Q3 on) V_OL ≤ 0.5V (Q4 on)