74LS04 INTERNAL SCHEMATIC — TTL INVERTER (NOT GATE) VCC +5V GND IN D1 Schottky clamp R1 8kΩ R2 8kΩ R3 1.5kΩ Q1 NPN Phase Splitter Q2 NPN Totem Top R4 120Ω D2 Schottky OUT Q3 NPN Totem Bottom IN=HIGH → Q1 ON → Q2 OFF, Q3 ON → OUT=LOW IN=LOW → Q1 OFF → Q2 ON, Q3 OFF → OUT=HIGH V_OH ≥ 2.7V | V_OL ≤ 0.5V | V_IH ≥ 2.0V | V_IL ≤ 0.8V t_pd ≈ 9ns | I_OH = -0.4mA | I_OL = 8mA | P_d ≈ 2mW/gate Schottky diodes prevent saturation → faster switching TOTEM-POLE OUTPUT STAGE Q2 + D2 + Q3 © Schematic for educational use — 74LS04 Hex Inverter, one of six identical gates per package